In recent years, an operating voltage of a semiconductor device is gradually decreasing for the purposes of reducing consumption power, and at present, a very low voltage of as low as 1 bolt is sometimes used. When the operating voltage decreases, a threshold voltage of a transistor needs to be decreased. Thus, there occurs a problem in that a sub-threshold current of a transistor in an off state increases. To solve such a problem, a method of dividing a power supply wiring into a main power supply wiring and a pseudo power supply wiring is proposed in Japanese Patent Application Laid-open Nos. 2000-13215 and 2000-48568.
FIG. 15 is a circuit diagram of a general semiconductor device using a pseudo power supply wiring.
A circuit shown in FIG. 15 includes a circuit block 10 formed of 4-stage inverters 11 to 14. In the circuit block 10, a logic value is fixed in a standby state, and in this example, its input signal IN is fixed to a high level in the standby state. Needless to say, in an active state, a logical value of the input signal IN varies as needed.
In the circuit shown in FIG. 15, four power supply wirings, that is, a main power supply wiring VDD and a pseudo power supply wiring VDDZ to which a power supply potential is supplied; and a main power supply wiring VSS and a pseudo power supply wiring VSSZ to which a ground potential is supplied are arranged. Between the main power supply wiring VDD and the pseudo power supply wiring VDDZ, a P-channel MOS transistor 21 is arranged, and its gate electrode is supplied with a stand by signal ST. Between the main power supply wiring VSS and the pseudo power supply wiring VSSZ, an N-channel MOS transistor 22 is arranged, and its gate electrode is supplied with a signal obtained by inverting the standby signal ST by an inverter 23.
The standby signal ST becomes a high level when the circuit block 10 is rendered the standby state, and remains a low level when the circuit block 10 is in the active state. Thus, in the active state, the main power supply wiring VDD and the pseudo power supply wiring VDDZ are short-circuited via the transistor 21, and the main power supply wiring VSS and the pseudo power supply wiring VSSZ are short-circuited via the transistor 22. On the other hand, in the standby state, both the transistors 21 and 22 are kept in an off state. Thus, the pseudo power supply wirings VDDZ and VSSZ are disconnected from the main power supply wirings VDD and VSS, respectively, and as a result, nearly no power supply potential is supplied.
Out of the four inverters 11 to 14 included in the circuit block 10, the first-stage inverter 11 and the third-stage inverter 13 are connected between the pseudo power supply wiring VDDZ and the main power supply wiring VSS, and the second-stage inverter 12 and the fourth-stage inverter 14 are connected between the main power supply wiring VDD and the pseudo power supply wiring VSSZ. As described above, in the active state, the main power supply wiring VDD and the pseudo power supply wiring VDDZ are short-circuited, and the main power supply wiring VSS and the pseudo power supply wiring VSSZ are short-circuited. Thus, a power supply voltage is correctly applied to both power supply terminals of all the inverters 11 to 14. As a result, the circuit block 10 can operate correctly, and an output signal OUT of the circuit block 10 is rendered a correct value according to a logical value of the input signal IN.
On the contrary, in the standby state, the pseudo power supply wiring VDDZ is disconnected from the main power supply wiring VDD, and the pseudo power supply wiring VSSZ is disconnected from the main power supply wiring VSS. Thus, sources of P-channel MOS transistors 11p and 13p included in the first-stage inverter 11 and the third-stage inverter 13 are supplied with nearly no power supply potential, and sources of N-channel MOS transistors 12n and 14n included in the second-stage inverter 12 and the fourth-stage inverter 14 are supplied with nearly no power supply potential.
However, in the standby state, the input signal IN is fixed to the high level. The transistors rendered conducting in the respective inverters 11 to 14 are fixed to an N-channel MOS transistor 11n, a P-channel MOS transistor 12p, an N-channel MOS transistor 13n, and a P-channel MOS transistor 14p shown in FIG. 15, respectively. Sources of these transistors are connected to the main power supply wiring VDD or the main power supply wiring VSS, and thus, the logic value in the standby state is kept correctly.
On the other hand, sources of the P-channel MOS transistors 11p and 13p rendered non-conducting in the standby state are connected to the pseudo power supply wiring VDDZ disconnected from the main power supply wiring VDD. As a result, nearly no sub-threshold current is passed. Likewise, sources of the N-channel MOS transistors 12n and 14n rendered non-conducting in the standby state are connected to the pseudo power supply wiring VSSZ disconnected from the main power supply wiring VSS. As a result, nearly no sub-threshold current is passed. Thereby, it becomes possible to reduce the power consumption in the standby state of the circuit block 10.
FIG. 16 is a circuit diagram for explaining a method of connecting with the pseudo power supply wiring when the input signal is complementary.
As shown in FIG. 16, when complementary input signals IN and INB are used, it is possible that circuit configurations of inverters 31, 32, 33, 34, . . . through which the input signal IN rendered the high level in the standby state passes and those of inverters 41, 42, 43, 44, . . . through which the input signal INB rendered the low level in the standby state passes are identical, and with this state, connection relationships to the main power supply wiring and the pseudo power supply wiring are inverted.
Specifically, regarding the inverters 31, 32, 33, 34, . . . through which the input signal IN passes, it is possible that the inverters 31, 33, . . . at the odd-numbered stages (a first stage, a third stage, . . . ) are connected between the pseudo power supply wiring VDDZ and the main power supply wiring VSS, and the inverters 32, 34, . . . at even-numbered stages (a second stage, a fourth stage, . . . ) are connected between the main power supply wiring VDD and the pseudo power supply wiring VSSZ. On the other hand, regarding the inverters 41, 42, 43, 44, . . . through which the input signal INB passes, it is possible that the inverters 41, 43, . . . at the odd-numbered stages (a first stage, a third stage, . . . ) are connected between the main power supply wiring VDD and the pseudo power supply wiring VSSZ, and the inverters 42, 44, . . . at even-numbered stages (a second stage, a fourth stage, . . . ) are connected between the pseudo power supply wiring VDDZ and the main power supply wiring VSS.
Thereby, in both the inverters 31, 32, 33, 34, through which the input signal IN passes and the inverters 41, 42, 43, 44, . . . through which the input signal INB passes, its transistors brought into an off state in the standby state are connected to the pseudo power supply wiring. Thus, it becomes possible to reduce the sub-threshold current.
However, in some products, paths to which the complementary input signals IN and INB are supplied are commonly supplied with an enable signal in some cases. For example, in a DRAM (Dynamic Random Access Memory) , there are cases where adopted is a configuration such that when a fuse is cut at the time of production to fix the enable signal to one logical level, a data input/output width is 16 bits, for example, and when the fuse remains uncut to fix the enable signal to the other logical level, the data input/output width is 8 bits, for example. In such case, a common enable signal is supplied to the both paths to which the complementary input signals IN and INB are supplied, and thus, this leads to a case where the sub-threshold current in the standby state is often increased.
FIG. 17 is a circuit diagram showing an example in which the enable signal is supplied to a path through which the complementary input signal passes.
A circuit shown in FIG. 17 differs from that shown in FIG. 16 in that the first-stage inverters 31 and 41 shown in FIG. 16 are replaced by NAND circuits 51 and 61. Input nodes on one side of the NAND circuits 51 and 61 are supplied with the input signals IN and INB, respectively, and input nodes on the other side are commonly supplied with an enable signal E. Thereby, when the enable signal E is the high level (when the data input/output width is 16 bits, for example) , two paths shown in FIG. 17 are rendered effective. On the other hand, when the enable signal E is the low level (when the data input/output width is 8 bits, for example), the two paths shown in FIG. 17 are rendered ineffective, and irrespective of logical levels of the input signals IN and INB, output is fixed.
The circuit shown in FIG. 17 is equivalent to that shown in FIG. 16 when the enable signal E is the high level, and thus, there occurs no problem. However, when the enable signal E is the low level, a connection relationship to the main power supply wiring and the pseudo power supply wiring in the path through which the input signal IN passes is opposite to the connection originally required.
That is, when the enable signal E is the low level, outputs of the NAND circuit 51 and the inverters 32, 33, 34, . . . that configure the path are rendered the high level, the low level, the high level, the low level, . . . , respectively, and in the connection shown in FIG. 17, a transistor side to be turned on is connected to the pseudo power supply wiring and a transistor side to be turned off is connected to the main power supply wiring, and with this state, the connection is fixed. Thus, when the enable signal E is the low level, it is not possible to render pseudo power supply wiring non-conducting the in the standby state, and as a result, there occurs a problem that the sub-threshold current increases.
FIG. 18 is a circuit diagram showing an example in which the sub-threshold current is reduced by improving the circuit shown in FIG. 17.
A circuit shown in FIG. 18 differs from that shown in FIG. 17 in that the NAND circuit 51 shown in FIG. 17 is replaced by an NOR circuit 71 and in addition, an inverter 70 is added. The NOR circuit 71 is supplied with a signal obtained by inverting the enable signal E by the inverter 70. Thus, when the enable signal E is the low level or when the input signal IN is fixed to the high level by the standby, output of the NOR circuit 71 is always fixed to the low level. As a result, it becomes possible to solve the problem inherent in the circuit shown in FIG. 17.
However, in the circuit shown in FIG. 18, a path through which the input signal IN passes and that through which the input signal INB passes differ in the circuit configuration. Thus, it is probable that a symmetric property of waveforms of the signals that pass the two paths collapses. As a result, when a high symmetric property is required for the complementary signal as in the case of a DLL (Delayed Lock Loop) circuit used for a DRAM or the like, it is not appropriate to use the circuit shown in FIG. 18.